System LSI: Challenges and Opportunities

What will happen if we continue to scale a CMOS device? Gate controllability will be degraded. If gate oxide thickness is kept constant in order to suppress gate leakage, and if channel length is scaled further, potential of silicon surface near the source that is associated with VTH is lowered by depletion layer capacitance of the drain (CD), as well as gate capacitance (CG). When CD is not small enough compared to CG, MOSFET behaves like a resistor, not a transistor. In other words, MOSFET does not turn off sufficiently. On top of that, leakage from gate is rapidly increasing. It should be noted that Ioff dependence on temperature is diminishing as technology scales. This indicates that the leakage is caused by tunneling leakage that depends on barrier thickness, not height. In the 45nm technology node, Ioff will reach to an unacceptable level.